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authorTodor Tomov2017-08-08 15:30:10 +0200
committerMauro Carvalho Chehab2017-08-26 21:16:56 +0200
commitd226efcfd0422a6f0194feb3affa34affd8998b7 (patch)
treedae7394e178b0404d4e1804ef9711f68e32069c7 /Documentation/media/v4l-drivers
parentmedia: camss: vfe: Format conversion support using PIX interface (diff)
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media: doc: media/v4l-drivers: Qualcomm Camera Subsystem - PIX Interface
Update Qualcomm Camera Subsystem driver document for the PIX interface and format conversion support. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'Documentation/media/v4l-drivers')
-rw-r--r--Documentation/media/v4l-drivers/qcom_camss.rst46
1 files changed, 36 insertions, 10 deletions
diff --git a/Documentation/media/v4l-drivers/qcom_camss.rst b/Documentation/media/v4l-drivers/qcom_camss.rst
index 4707ea7b2f11..d8884436dae6 100644
--- a/Documentation/media/v4l-drivers/qcom_camss.rst
+++ b/Documentation/media/v4l-drivers/qcom_camss.rst
@@ -45,12 +45,36 @@ Supported functionality
The current version of the driver supports:
-- input from camera sensor via CSIPHY;
-- generation of test input data by the TG in CSID;
-- raw dump of the input data to memory. RDI interface of VFE is supported.
- PIX interface (ISP processing, statistics engines, resize/crop, format
- conversion) is not supported in the current version;
-- concurrent and independent usage of two data inputs - could be camera sensors
+- Input from camera sensor via CSIPHY;
+- Generation of test input data by the TG in CSID;
+- RDI interface of VFE - raw dump of the input data to memory.
+
+ Supported formats:
+
+ - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
+ V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY);
+ - MIPI RAW8 (8bit Bayer RAW - V4L2_PIX_FMT_SRGGB8 /
+ V4L2_PIX_FMT_SGRBG8 / V4L2_PIX_FMT_SGBRG8 / V4L2_PIX_FMT_SBGGR8);
+ - MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P /
+ V4L2_PIX_FMT_SGBRG10P / V4L2_PIX_FMT_SGRBG10P / V4L2_PIX_FMT_SRGGB10P);
+ - MIPI RAW12 (12bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB12P /
+ V4L2_PIX_FMT_SGBRG12P / V4L2_PIX_FMT_SGRBG12P / V4L2_PIX_FMT_SRGGB12P).
+
+- PIX interface of VFE
+
+ - Format conversion of the input data.
+
+ Supported input formats:
+
+ - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
+ V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY).
+
+ Supported output formats:
+
+ - NV12/NV21 (two plane YUV 4:2:0 - V4L2_PIX_FMT_NV12 / V4L2_PIX_FMT_NV21);
+ - NV16/NV61 (two plane YUV 4:2:2 - V4L2_PIX_FMT_NV16 / V4L2_PIX_FMT_NV61).
+
+- Concurrent and independent usage of two data inputs - could be camera sensors
and/or TG.
@@ -65,15 +89,15 @@ interface, the driver is split into V4L2 sub-devices as follows:
- 2 CSID sub-devices - each CSID is represented by a single sub-device;
- 2 ISPIF sub-devices - ISPIF is represented by a number of sub-devices equal
to the number of CSID sub-devices;
-- 3 VFE sub-devices - VFE is represented by a number of sub-devices equal to
- the number of RDI input interfaces.
+- 4 VFE sub-devices - VFE is represented by a number of sub-devices equal to
+ the number of the input interfaces (3 RDI and 1 PIX).
The considerations to split the driver in this particular way are as follows:
- representing CSIPHY and CSID modules by a separate sub-device for each module
allows to model the hardware links between these modules;
-- representing VFE by a separate sub-devices for each RDI input interface allows
- to use the three RDI interfaces concurently and independently as this is
+- representing VFE by a separate sub-devices for each input interface allows
+ to use the input interfaces concurently and independently as this is
supported by the hardware;
- representing ISPIF by a number of sub-devices equal to the number of CSID
sub-devices allows to create linear media controller pipelines when using two
@@ -99,6 +123,8 @@ nodes) is as follows:
- msm_vfe0_video1
- msm_vfe0_rdi2
- msm_vfe0_video2
+- msm_vfe0_pix
+- msm_vfe0_video3
Implementation