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authorDave Airlie2016-07-22 03:40:24 +0200
committerDave Airlie2016-07-22 03:40:24 +0200
commitc11dea5b0290984fa48111957ba3fdc5b3bdae5a (patch)
tree0bbdd88c17e5624f5ef8bbe395593f65300ffa5a /Documentation
parentMerge branch 'drm-rockchip-next-fixes-2016-07-19' of https://github.com/marky... (diff)
parentdrm/fsl-dcu: add support for drm bridge (diff)
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Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next
This adds drm bridge support for the NXP/Freescale DCU. The patchset has been discussed on the mailing list since quite some time... Plus there is a small fix provided by Peter. * 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu: drm/fsl-dcu: add support for drm bridge drm/fsl-dcu: rework codes to support of_graph dt binding for panel drm/fsl-dcu: add missing of_node_put after calling of_parse_phandle
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/display/fsl,dcu.txt9
1 files changed, 7 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ae55cde1b69e..63ec2a624aa9 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -12,7 +12,7 @@ Required properties:
- clock-names: Should be "dcu" and "pix"
See ../clocks/clock-bindings.txt for details.
- big-endian Boolean property, LS1021A DCU registers are big-endian.
-- fsl,panel: The phandle to panel node.
+- port Video port for the panel output
Optional properties:
- fsl,tcon: The phandle to the timing controller node.
@@ -24,6 +24,11 @@ dcu: dcu@2ce0000 {
clocks = <&platform_clk 0>, <&platform_clk 0>;
clock-names = "dcu", "pix";
big-endian;
- fsl,panel = <&panel>;
fsl,tcon = <&tcon>;
+
+ port {
+ dcu_out: endpoint {
+ remote-endpoint = <&panel_out>;
+ };
+ };
};