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| author | Mark Salter | 2011-10-04 17:20:28 +0200 |
|---|---|---|
| committer | Mark Salter | 2011-10-07 01:48:36 +0200 |
| commit | 9de98fb4ec4c91597feedc521120c16fca54a5b6 (patch) | |
| tree | bb956a3946cf547d82edf854bdfc960126f31c4b /MAINTAINERS | |
| parent | C6X: EMIF - External Memory Interface (diff) | |
| download | kernel-qcow2-linux-9de98fb4ec4c91597feedc521120c16fca54a5b6.tar.gz kernel-qcow2-linux-9de98fb4ec4c91597feedc521120c16fca54a5b6.tar.xz kernel-qcow2-linux-9de98fb4ec4c91597feedc521120c16fca54a5b6.zip | |
C6X: DSCR - Device State Configuration Registers
All SoCs provide an area of device configuration registers called the DSCR. The
location of specific registers as well as their use varies considerably from
implementation to implementation. Rather than having to rely on additional
SoC-specific DSCR code for each new supported SoC, this code generalize things
as much as possible using device tree properties. Initialization must take
place early on (setup_arch time) in case the event timer device needs to be
enable via the DSCR.
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'MAINTAINERS')
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