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| author | Steven J. Hill | 2013-11-14 17:12:24 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-22 20:18:58 +0100 |
| commit | 4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b (patch) | |
| tree | 316ae10e4705f42a0690d44254be218c4bedbc03 /README | |
| parent | MIPS: features: Add initial support for TLBINVF capable cores (diff) | |
| download | kernel-qcow2-linux-4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b.tar.gz kernel-qcow2-linux-4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b.tar.xz kernel-qcow2-linux-4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b.zip | |
MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
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