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| author | Vineet Gupta | 2013-05-28 11:54:30 +0200 |
|---|---|---|
| committer | Vineet Gupta | 2013-06-22 15:53:23 +0200 |
| commit | 1898a959b7512fcf6fa9f436ac8c403fab7255c3 (patch) | |
| tree | e990d920414c458af317afb08f53c7f9e05404b3 /arch/arc/include/asm/arcregs.h | |
| parent | ARC: Increase readability of entry handlers (diff) | |
| download | kernel-qcow2-linux-1898a959b7512fcf6fa9f436ac8c403fab7255c3.tar.gz kernel-qcow2-linux-1898a959b7512fcf6fa9f436ac8c403fab7255c3.tar.xz kernel-qcow2-linux-1898a959b7512fcf6fa9f436ac8c403fab7255c3.zip | |
ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR values
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/arcregs.h')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 6addeec34a7c..122e9af46824 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -68,6 +68,11 @@ #define ECR_C_PROTV_XCHG 0x03 #define ECR_C_PROTV_MISALIG_DATA 0x04 +#define ECR_C_BIT_PROTV_MISALIG_DATA 10 + +/* Machine Check Cause Code Values */ +#define ECR_C_MCHK_DUP_TLB 0x01 + /* DTLB Miss Exception Cause Code Values */ #define ECR_C_BIT_DTLB_LD_MISS 8 #define ECR_C_BIT_DTLB_ST_MISS 9 |