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| author | Javier Martinez Canillas | 2014-09-13 17:47:22 +0200 |
|---|---|---|
| committer | Kukjin Kim | 2014-09-13 17:47:22 +0200 |
| commit | 8be6a6d04ceae15de160ca4cbc0915baaee801e4 (patch) | |
| tree | ea6b6ea245b378d977f59f7677bf0ce168522be8 /arch/arm/boot/dts/exynos5800-peach-pi.dts | |
| parent | ARM: dts: Add ISL29018 sensor for exynos based Peach boards (diff) | |
| download | kernel-qcow2-linux-8be6a6d04ceae15de160ca4cbc0915baaee801e4.tar.gz kernel-qcow2-linux-8be6a6d04ceae15de160ca4cbc0915baaee801e4.tar.xz kernel-qcow2-linux-8be6a6d04ceae15de160ca4cbc0915baaee801e4.zip | |
ARM: dts: Set i2c7 clock at 400kHz for exynos based Peach boards
The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.
Suggested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5800-peach-pi.dts')
| -rw-r--r-- | arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 17537f0ab44a..88b354452d2f 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -487,6 +487,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98091: codec@10 { compatible = "maxim,max98091"; |