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| author | Linus Walleij | 2017-11-19 11:04:23 +0100 |
|---|---|---|
| committer | Linus Walleij | 2018-01-17 00:26:50 +0100 |
| commit | 95220046a62c00b5afb1aa7c1971989d427db977 (patch) | |
| tree | e4eeac48eea01d281fe3eb06c92358902e357f2c /arch/arm/boot/dts/gemini-rut1xx.dts | |
| parent | ARM: dts: Add ethernet to the Gemini SoC (diff) | |
| download | kernel-qcow2-linux-95220046a62c00b5afb1aa7c1971989d427db977.tar.gz kernel-qcow2-linux-95220046a62c00b5afb1aa7c1971989d427db977.tar.xz kernel-qcow2-linux-95220046a62c00b5afb1aa7c1971989d427db977.zip | |
ARM: dts: Add ethernet to a bunch of platforms
These platforms have the PHY defined already so we just
need to add a single device node to each of them to activate
the ethernet device.
The PHY skew/delay settings for pin control is known from a
few vendor trees and old OpenWRT patch sets.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/gemini-rut1xx.dts')
| -rw-r--r-- | arch/arm/boot/dts/gemini-rut1xx.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index fd55528bba56..15f20178642c 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -114,5 +114,17 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_default_pins>; }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; }; }; |