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author | Linus Torvalds | 2014-08-08 20:14:29 +0200 |
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committer | Linus Torvalds | 2014-08-08 20:14:29 +0200 |
commit | b3345d7c57d70e6cb6749af25cdbe80515582e99 (patch) | |
tree | 04cce706bc7e944ad1fb257108a8ae735948f97f /arch/arm/boot/dts/hisi-x5hd2.dtsi | |
parent | Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git... (diff) | |
parent | ARM: hisi: remove smp from machine descriptor (diff) | |
download | kernel-qcow2-linux-b3345d7c57d70e6cb6749af25cdbe80515582e99.tar.gz kernel-qcow2-linux-b3345d7c57d70e6cb6749af25cdbe80515582e99.tar.xz kernel-qcow2-linux-b3345d7c57d70e6cb6749af25cdbe80515582e99.zip |
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This is the bulk of new SoC enablement and other platform changes for
3.17:
- Samsung S5PV210 has been converted to DT and multiplatform
- Clock drivers and bindings for some of the lower-end i.MX 1/2
platforms
- Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood
- Hwmod data for TI AM43xx and DRA7 platforms
- More additions of Renesas shmobile platform support
- Removal of plat-samsung contents that can be removed with S5PV210
being multiplatform/DT-enabled and the other two old platforms
being removed
New platforms (most with only basic support right now):
- Hisilicon X5HD2 settop box chipset is introduced
- Mediatek MT6589 (mobile chipset) is introduced
- Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code"
* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
ARM: hisi: remove smp from machine descriptor
power: reset: move hisilicon reboot code
ARM: dts: Add hix5hd2-dkb dts file.
ARM: debug: Rename Hi3716 to HIX5HD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: add ARCH_HISI
MAINTAINERS: add entry for Broadcom ARM STB architecture
ARM: brcmstb: select GISB arbiter and interrupt drivers
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
ARM: configs: enable SMP in bcm_defconfig
ARM: add SMP support for Broadcom mobile SoCs
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
...
Diffstat (limited to 'arch/arm/boot/dts/hisi-x5hd2.dtsi')
-rw-r--r-- | arch/arm/boot/dts/hisi-x5hd2.dtsi | 170 |
1 files changed, 170 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi new file mode 100644 index 000000000000..f85ba2924ff7 --- /dev/null +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2013-2014 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/hix5hd2-clock.h> + +/ { + aliases { + serial0 = &uart0; + }; + + gic: interrupt-controller@f8a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0xf8000000 0x8000000>; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + ranges; + + timer0: timer@00002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00002000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 24 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer1: timer@00a29000 { + /* + * Only used in NORMAL state, not available ins + * SLOW or DOZE state. + * The rate is fixed in 24MHz. + */ + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a29000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 25 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer2: timer@00a2a000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2a000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 26 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer3: timer@00a2b000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2b000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 27 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer4: timer@00a81000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a81000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 28 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + uart0: uart@00b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b00000 0x1000>; + interrupts = <0 49 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@00006000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00006000 0x1000>; + interrupts = <0 50 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@00b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b02000 0x1000>; + interrupts = <0 51 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart3: uart@00b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b03000 0x1000>; + interrupts = <0 52 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart4: uart@00b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb04000 0x1000>; + interrupts = <0 53 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + + local_timer@00a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + l2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x00a10000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + }; + + sysctrl: system-controller@00000000 { + compatible = "hisilicon,sysctrl"; + reg = <0x00000000 0x1000>; + reboot-offset = <0x4>; + }; + + cpuctrl@00a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; + }; +}; |