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| author | Andrey Smirnov | 2018-07-13 19:30:04 +0200 |
|---|---|---|
| committer | Shawn Guo | 2018-07-17 08:45:39 +0200 |
| commit | a1a30f892894ff27b747a04d032fee72ade1bdca (patch) | |
| tree | 9e2de7b8d1218e6b2293a572c6d8e24b76e92af5 /arch/arm/boot/dts/imx51-zii-scu3-esb.dts | |
| parent | ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration (diff) | |
| download | kernel-qcow2-linux-a1a30f892894ff27b747a04d032fee72ade1bdca.tar.gz kernel-qcow2-linux-a1a30f892894ff27b747a04d032fee72ade1bdca.tar.xz kernel-qcow2-linux-a1a30f892894ff27b747a04d032fee72ade1bdca.zip | |
ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
Instead of relying on default values, configure PAD_AUD3_BB_CK to be a
GPIO explicitly. While at, it change the pad configuration to enable
a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH).
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: cphealy@gmail.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx51-zii-scu3-esb.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 07bc5fc05076..a7ede537e12a 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |