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| author | Valentin Raevsky | 2016-06-13 01:24:55 +0200 |
|---|---|---|
| committer | Shawn Guo | 2016-06-16 03:32:37 +0200 |
| commit | 5bca20f7fe003c65009b4d49cd13630827dae691 (patch) | |
| tree | 2f812215111e89d18984fdd9da6bdfb1d7316858 /arch/arm/boot/dts/imx6q-cm-fx6.dts | |
| parent | ARM: dts: imx6qdl.dtsi: add "arm,shared-override" for pl310 (diff) | |
| download | kernel-qcow2-linux-5bca20f7fe003c65009b4d49cd13630827dae691.tar.gz kernel-qcow2-linux-5bca20f7fe003c65009b4d49cd13630827dae691.tar.xz kernel-qcow2-linux-5bca20f7fe003c65009b4d49cd13630827dae691.zip | |
ARM: dts: imx6q-cm-fx6: fix the operation points
The current ldo settings of the cm-fx6 do not allow 1.2GHz cpu
frequency. At this frequency the module behaves unstable.
But the imx6q fuse indicates that 1.2GHz operation is possible.
Hence, remove the 1.2GHz operation point in the device tree.
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
[christopher.spinrath@rwth-aachen.de: enhance commit message, adjust
remaining operation points to match the ones in imx6q.dtsi and add
a comment in the device tree]
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-cm-fx6.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-cm-fx6.dts | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 6d8d5e98b7c2..b5de7e620905 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -91,6 +91,28 @@ }; }; +&cpu0 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; |