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| author | Santosh Shilimkar | 2012-07-04 15:02:32 +0200 |
|---|---|---|
| committer | Benoit Cousson | 2012-09-07 19:18:43 +0200 |
| commit | eed0de27726a55f145490619510c8ec58c9dc767 (patch) | |
| tree | 76cd4609a74b50cbc059eefb30a65dd2aee0118c /arch/arm/boot/dts/omap4.dtsi | |
| parent | ARM: OMAP4: Add L2 Cache Controller in Device Tree (diff) | |
| download | kernel-qcow2-linux-eed0de27726a55f145490619510c8ec58c9dc767.tar.gz kernel-qcow2-linux-eed0de27726a55f145490619510c8ec58c9dc767.tar.xz kernel-qcow2-linux-eed0de27726a55f145490619510c8ec58c9dc767.zip | |
ARM: OMAP4: Add local timer support for Device Tree
Add cortex-a9 local timer support for all OMAP4 based
SOCs using DT.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index cb18d2a2971c..2b670ab86eae 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -45,6 +45,12 @@ cache-level = <2>; }; + local-timer@0x48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x20>; + interrupts = <1 13 0x304>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. |