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| author | Heiko Stuebner | 2015-08-02 22:29:33 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2015-08-08 12:25:32 +0200 |
| commit | ec32bd9fcadc26d8a184c9a09ec3fe29e097c175 (patch) | |
| tree | ffdcc9ba1af25e11d6b7ca127f4111d13a6bb860 /arch/arm/boot/dts/rk3xxx.dtsi | |
| parent | ARM: dts: rockchip: Add veyron-speedy board (diff) | |
| download | kernel-qcow2-linux-ec32bd9fcadc26d8a184c9a09ec3fe29e097c175.tar.gz kernel-qcow2-linux-ec32bd9fcadc26d8a184c9a09ec3fe29e097c175.tar.xz kernel-qcow2-linux-ec32bd9fcadc26d8a184c9a09ec3fe29e097c175.zip | |
ARM: dts: rockchip: set correct dwc2 params for cortex-a9 socs
According to the manual, the fifo sizes are the same as on later socs
like the rk3288 and this also fixes an error about "insufficient fifo
memory", as it seems the values read from the ip are wrong.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3xxx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3xxx.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index a2ae9f32464d..c571ac87a4ff 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -172,6 +172,11 @@ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; status = "disabled"; }; @@ -181,6 +186,7 @@ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG1>; clock-names = "otg"; + dr_mode = "host"; status = "disabled"; }; |