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| author | Thor Thayer | 2017-02-02 23:05:21 +0100 |
|---|---|---|
| committer | Dinh Nguyen | 2017-02-03 04:33:47 +0100 |
| commit | cda1ade6a25c85d0a7cc2001a96b0b20f6bfd3f0 (patch) | |
| tree | f7c606b3621b112b8447de51c80c313c7ba79745 /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | ARM: dts: watchdog0 cannot reliably trigger reset (diff) | |
| download | kernel-qcow2-linux-cda1ade6a25c85d0a7cc2001a96b0b20f6bfd3f0.tar.gz kernel-qcow2-linux-cda1ade6a25c85d0a7cc2001a96b0b20f6bfd3f0.tar.xz kernel-qcow2-linux-cda1ade6a25c85d0a7cc2001a96b0b20f6bfd3f0.zip | |
ARM: dts: Add EMAC AXI settings for Arria10
Add the device tree entries needed to support the EMAC AXI
bus settings on the Arria10 SoCFPGA chip.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 65904db153be..6b0b7463f36f 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -408,6 +408,12 @@ }; }; + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x44 0>; @@ -424,6 +430,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -443,6 +450,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,6 +468,7 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; |