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authorLinus Walleij2014-02-03 23:16:49 +0100
committerLinus Walleij2014-02-04 20:50:50 +0100
commit7acacfbc3d68c4d431ee44ae7db81c3f5e37b41c (patch)
tree0f9bb880918f6c0539e77a6d20cb61df198afdbc /arch/arm/boot/dts/ste-href-ab8500.dtsi
parentARM: ux500: move AB8500 modem I2C settings to DT (diff)
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ARM: ux500: move AB8500 clock out pins to DT
This moves the AB8500 pin settings for the clock out pins over to the device tree. We can delete the special setup calls for the platforms only using the AB8500 and not AB8505. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-href-ab8500.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-href-ab8500.dtsi51
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 333b554c0bf7..30f8601da323 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -370,6 +370,57 @@
};
};
};
+ /*
+ * Clock output pins associated with regulators.
+ */
+ sysclkreq2 {
+ sysclkreq2_default_mode: sysclkreq2_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_T10";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq2_sleep_mode: sysclkreq2_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio1_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_T10";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ sysclkreq4 {
+ sysclkreq4_default_mode: sysclkreq4_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq4_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_U9";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq4_sleep_mode: sysclkreq4_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio3_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_U9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};