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| author | Maxime Ripard | 2014-02-05 14:05:06 +0100 |
|---|---|---|
| committer | Maxime Ripard | 2014-02-07 20:22:52 +0100 |
| commit | 0d6efe339e21eb29802556398287187213b4f1f0 (patch) | |
| tree | 578d1e30a0d40c91124160409f080945bea0941a /arch/arm/boot/dts/sun6i-a31.dtsi | |
| parent | ARM: sun6i: dt: Add PLL6 and SPI module clocks (diff) | |
| download | kernel-qcow2-linux-0d6efe339e21eb29802556398287187213b4f1f0.tar.gz kernel-qcow2-linux-0d6efe339e21eb29802556398287187213b4f1f0.tar.xz kernel-qcow2-linux-0d6efe339e21eb29802556398287187213b4f1f0.zip | |
ARM: sun6i: dt: Add SPI controllers to the A31 DTSI
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 93d7bb6b1697..fc07f7089b85 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -350,6 +350,46 @@ status = "disabled"; }; + spi0: spi@01c68000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <0 65 4>; + clocks = <&ahb1_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 20>; + status = "disabled"; + }; + + spi1: spi@01c69000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c69000 0x1000>; + interrupts = <0 66 4>; + clocks = <&ahb1_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 21>; + status = "disabled"; + }; + + spi2: spi@01c6a000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6a000 0x1000>; + interrupts = <0 67 4>; + clocks = <&ahb1_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 22>; + status = "disabled"; + }; + + spi3: spi@01c6b000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6b000 0x1000>; + interrupts = <0 68 4>; + clocks = <&ahb1_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 23>; + status = "disabled"; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, |