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| author | Maxime Ripard | 2014-04-17 11:06:46 +0200 |
|---|---|---|
| committer | Daniel Lezcano | 2014-04-22 13:56:50 +0200 |
| commit | 8cffcb0ca33381e07cee4ebe1301d0794054fc97 (patch) | |
| tree | f4eab12ecd620b78dfed2a1e2331c1e3e62b0bfd /arch/arm/boot/dts/sun6i-a31.dtsi | |
| parent | clocksource: sun5i: Add support for reset controller (diff) | |
| download | kernel-qcow2-linux-8cffcb0ca33381e07cee4ebe1301d0794054fc97.tar.gz kernel-qcow2-linux-8cffcb0ca33381e07cee4ebe1301d0794054fc97.tar.xz kernel-qcow2-linux-8cffcb0ca33381e07cee4ebe1301d0794054fc97.zip | |
ARM: sun6i: a31: Add support for the High Speed Timers
The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.
Now that we have a driver to support it, we can enable them in the
device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..8cee8a15b90b 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -428,6 +428,17 @@ status = "disabled"; }; + timer@01c60000 { + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 51 4>, + <0 52 4>, + <0 53 4>, + <0 54 4>; + clocks = <&ahb1_gates 19>; + resets = <&ahb1_rst 19>; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; |