ARM: dts: vf610-zii-dev-c: Wire up PHY interrupts

The PHYs embedded in the switch direct there interrupts through the
switch interrupt controllers. Now that devel C has its switch
interrupts connected to the SoC, the PHY interrupts can be used by
phylib. Explicitly include MDIO nodes in the switch device tree nodes,
and link the PHY interrupts back to the switch interrupt
controller. Also, link the ports to the PHYs on the MDIO bus.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

1 files changed, 65 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 352ecec64bb7..db3b408ea55a 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -97,21 +97,25 @@
 					port@1 {
 						reg = <1>;
 						label = "lan1";
+						phy-handle = <&switch0phy1>;
 					};
 
 					port@2 {
 						reg = <2>;
 						label = "lan2";
+						phy-handle = <&switch0phy2>;
 					};
 
 					port@3 {
 						reg = <3>;
 						label = "lan3";
+						phy-handle = <&switch0phy3>;
 					};
 
 					port@4 {
 						reg = <4>;
 						label = "lan4";
+						phy-handle = <&switch0phy4>;
 					};
 
 					switch0port10: port@10 {
@@ -121,6 +125,35 @@
 						link = <&switch1port10>;
 					};
 				};
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					switch0phy1: switch0phy@1 {
+						reg = <1>;
+						interrupt-parent = <&switch0>;
+						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch0phy2: switch0phy@2 {
+						reg = <2>;
+						interrupt-parent = <&switch0>;
+						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch0phy3: switch0phy@3 {
+						reg = <3>;
+						interrupt-parent = <&switch0>;
+						interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch0phy4: switch0phy@4 {
+						reg = <4>;
+						interrupt-parent = <&switch0>;
+						interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+					};
+				};
 			};
 		};
 
@@ -150,21 +183,25 @@
 					port@1 {
 						reg = <1>;
 						label = "lan5";
+						phy-handle = <&switch1phy1>;
 					};
 
 					port@2 {
 						reg = <2>;
 						label = "lan6";
+						phy-handle = <&switch1phy2>;
 					};
 
 					port@3 {
 						reg = <3>;
 						label = "lan7";
+						phy-handle = <&switch1phy3>;
 					};
 
 					port@4 {
 						reg = <4>;
 						label = "lan8";
+						phy-handle = <&switch1phy4>;
 					};
 
 
@@ -175,6 +212,34 @@
 						link = <&switch0port10>;
 					};
 				};
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					switch1phy1: switch1phy@1 {
+						reg = <1>;
+						interrupt-parent = <&switch1>;
+						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch1phy2: switch1phy@2 {
+						reg = <2>;
+						interrupt-parent = <&switch1>;
+						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch1phy3: switch1phy@3 {
+						reg = <3>;
+						interrupt-parent = <&switch1>;
+						interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+					};
+
+					switch1phy4: switch1phy@4 {
+						reg = <4>;
+						interrupt-parent = <&switch1>;
+						interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+					};
+				};
 			};
 		};