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| author | Marek Szyprowski | 2019-05-28 10:38:14 +0200 |
|---|---|---|
| committer | Russell King | 2019-06-20 23:29:58 +0200 |
| commit | 5f41f9198f296091c6a58bc2e86af1e9f019b2a3 (patch) | |
| tree | f309f6b56520b0b974c46cff4de32b3d8decc1c1 /arch/arm/configs | |
| parent | ARM: 8861/1: errata: Workaround errata A12 857271 / A17 857272 (diff) | |
| download | kernel-qcow2-linux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.tar.gz kernel-qcow2-linux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.tar.xz kernel-qcow2-linux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.zip | |
ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores
Some big.LITTLE systems have I-Cache line size mismatch between
LITTLE and big cores. This patch adds a workaround for proper I-Cache
support on such systems. Without it, some class of the userspace code
(typically self-modifying) might suffer from random SIGILL failures.
Similar workaround already exists for ARM64 architecture. I has been
added by commit 116c81f427ff ("arm64: Work around systems with mismatched
cache line sizes").
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/configs')
| -rw-r--r-- | arch/arm/configs/exynos_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index c95c54284da2..9b959afaaa12 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS3=y +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y CONFIG_SMP=y CONFIG_BIG_LITTLE=y CONFIG_NR_CPUS=8 |