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authorRob Herring2011-09-29 04:27:52 +0200
committerArnd Bergmann2011-10-31 14:03:26 +0100
commitb3f7ed0324091e2cb23fe1b3c10570700f614014 (patch)
tree6f9a14a39fc4302276a1560cb48c1ede72fc5dff /arch/arm/include/asm/hardware/gic.h
parentARM: gic: add irq_domain support (diff)
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ARM: gic: add OF based initialization
This adds ARM gic interrupt controller initialization using device tree data. The initialization function is intended to be called by of_irq_init function like this: const static struct of_device_id irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, {} }; static void __init init_irqs(void) { of_irq_init(irq_match); } Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/arm/include/asm/hardware/gic.h')
-rw-r--r--arch/arm/include/asm/hardware/gic.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 43a05d90e43b..0a026b9290f2 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -40,6 +40,7 @@ extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);