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| author | Will Deacon | 2012-07-29 13:36:28 +0200 |
|---|---|---|
| committer | Will Deacon | 2012-08-23 12:35:52 +0200 |
| commit | 6dbc00297095122ea89e016ce6affad0b7c0ddac (patch) | |
| tree | f3c01a92818dd1a8e9cf9cd9a52cae8229332c55 /arch/arm/include/asm/pmu.h | |
| parent | ARM: perf: probe devicetree in preference to current CPU (diff) | |
| download | kernel-qcow2-linux-6dbc00297095122ea89e016ce6affad0b7c0ddac.tar.gz kernel-qcow2-linux-6dbc00297095122ea89e016ce6affad0b7c0ddac.tar.xz kernel-qcow2-linux-6dbc00297095122ea89e016ce6affad0b7c0ddac.zip | |
ARM: perf: prepare for moving CPU PMU code into separate file
The CPU PMU code is tightly coupled with generic ARM PMU handling code.
This makes it cumbersome when trying to add support for other ARM PMUs
(e.g. interconnect, L2 cache controller, bus) as the generic parts of
the code are not readily reusable.
This patch cleans up perf_event.c so that reusable code is exposed via
header files to other potential PMU drivers. The CPU code is
consistently named to identify it as such and also to prepare for moving
it into a separate file.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include/asm/pmu.h')
| -rw-r--r-- | arch/arm/include/asm/pmu.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index fbec73a0ee76..a993ad676047 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -89,7 +89,9 @@ struct arm_pmu { #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) -int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); +extern const struct dev_pm_ops armpmu_dev_pm_ops; + +int armpmu_register(struct arm_pmu *armpmu, char *name, int type); u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, @@ -99,6 +101,13 @@ int armpmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx); +int armpmu_map_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask); + #endif /* CONFIG_HW_PERF_EVENTS */ #endif /* __ARM_PMU_H__ */ |