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| author | Catalin Marinas | 2011-11-22 18:30:29 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2011-12-08 11:30:39 +0100 |
| commit | 1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001 (patch) | |
| tree | b04e3b1fd23ba81a643f64cba113551d127111a0 /arch/arm/include/asm/tlb.h | |
| parent | ARM: LPAE: Page table maintenance for the 3-level format (diff) | |
| download | kernel-qcow2-linux-1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001.tar.gz kernel-qcow2-linux-1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001.tar.xz kernel-qcow2-linux-1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001.zip | |
ARM: LPAE: MMU setup for the 3-level page table format
This patch adds the MMU initialisation for the LPAE page table format.
The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new
proc-v7-3level.S file contains the TTB initialisation, context switch
and PTE setting code with the LPAE. The TTBRx split is based on the
PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings
(supersections) and a few other memory types in mmu.c are conditionally
compiled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/include/asm/tlb.h')
0 files changed, 0 insertions, 0 deletions