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| author | Santosh Shilimkar | 2010-07-11 11:05:37 +0200 |
|---|---|---|
| committer | Santosh Shilimkar | 2010-10-26 08:10:03 +0200 |
| commit | 5ba70372289a1fb378b95cee2cf46b0203d65291 (patch) | |
| tree | 9f5fed0e160ff3476af12e51689cd6eeb9ae48a7 /arch/arm/include/asm | |
| parent | ARM: l2x0: Fix coding-style in the cache-l2x0.h (diff) | |
| download | kernel-qcow2-linux-5ba70372289a1fb378b95cee2cf46b0203d65291.tar.gz kernel-qcow2-linux-5ba70372289a1fb378b95cee2cf46b0203d65291.tar.xz kernel-qcow2-linux-5ba70372289a1fb378b95cee2cf46b0203d65291.zip | |
ARM: l2x0: Determine the cache size
The cache size is needed for to optimise range based
maintainance operations
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index d833355569cb..4633d2a8817a 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -55,6 +55,7 @@ #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); |