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author | Jean-Christophe PLAGNIOL-VILLARD | 2011-09-16 17:37:50 +0200 |
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committer | Jean-Christophe PLAGNIOL-VILLARD | 2011-11-28 15:50:37 +0100 |
commit | 80e91cb8023fbc07b2410c4ce5a2da12fbcebca4 (patch) | |
tree | c83ecd72567662ee3e59e35751c52b0f2293aa47 /arch/arm/mach-at91/include/mach/at91sam9rl.h | |
parent | ARM: at91: define CLOCK_TICK_RATE to bogus value except A91X40 (diff) | |
download | kernel-qcow2-linux-80e91cb8023fbc07b2410c4ce5a2da12fbcebca4.tar.gz kernel-qcow2-linux-80e91cb8023fbc07b2410c4ce5a2da12fbcebca4.tar.xz kernel-qcow2-linux-80e91cb8023fbc07b2410c4ce5a2da12fbcebca4.zip |
ARM: at91: make gpio register base soc independant
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Ryan Mallon <rmallon@gmail.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9rl.h')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 1aabacd315d4..d3ef11ad04df 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -77,10 +77,6 @@ #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) @@ -91,6 +87,11 @@ #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) +#define AT91SAM9RL_BASE_PIOA 0xfffff400 +#define AT91SAM9RL_BASE_PIOB 0xfffff600 +#define AT91SAM9RL_BASE_PIOC 0xfffff800 +#define AT91SAM9RL_BASE_PIOD 0xfffffa00 + #define AT91_USART0 AT91SAM9RL_BASE_US0 #define AT91_USART1 AT91SAM9RL_BASE_US1 #define AT91_USART2 AT91SAM9RL_BASE_US2 |