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| author | Tushar Behera | 2011-12-27 06:42:50 +0100 |
|---|---|---|
| committer | Kukjin Kim | 2012-03-11 07:51:12 +0100 |
| commit | 8f7b13218b01e287895c9906bca94f67f8bc25b9 (patch) | |
| tree | 06b22b9d4a020d9654338deea46da5677a5ed1eb /arch/arm/mach-exynos/clock-exynos4.c | |
| parent | ARM: EXYNOS: Enable MDMA driver (diff) | |
| download | kernel-qcow2-linux-8f7b13218b01e287895c9906bca94f67f8bc25b9.tar.gz kernel-qcow2-linux-8f7b13218b01e287895c9906bca94f67f8bc25b9.tar.xz kernel-qcow2-linux-8f7b13218b01e287895c9906bca94f67f8bc25b9.zip | |
ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1
Amba core assumes the pclk to be named as apb_pclk. During device probe,
it tries to get that clock and enable that. When PM_RUNTIME is enabled,
dma clock is not explicitly enabled in pl330_probe, which causes device
probe to fail. Adding a clkdev entry for apb_pclk for mdma1 fixes the
problem.
This patch fixes following runtime error.
dma-pl330 dma-pl330.2: PERIPH_ID 0x0, PCELL_ID 0x0 !
dma-pl330: probe of dma-pl330.2 failed with error -22
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
| -rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index db5d1cce3d25..1bc0b751520e 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1338,6 +1338,7 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), + CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), |