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| author | Santosh Shilimkar | 2013-06-14 01:24:39 +0200 |
|---|---|---|
| committer | Santosh Shilimkar | 2014-05-08 21:43:33 +0200 |
| commit | 5eb3da7246a5b2dfac9f38a7be62b1a0295584c7 (patch) | |
| tree | ac9e5b17b8691c1b0065cdb6289a8cce83c76bc5 /arch/arm/mach-keystone/platsmp.c | |
| parent | ARM: configs: keystone: add MTD_SPI_NOR (new dependency for M25P80) (diff) | |
| download | kernel-qcow2-linux-5eb3da7246a5b2dfac9f38a7be62b1a0295584c7.tar.gz kernel-qcow2-linux-5eb3da7246a5b2dfac9f38a7be62b1a0295584c7.tar.xz kernel-qcow2-linux-5eb3da7246a5b2dfac9f38a7be62b1a0295584c7.zip | |
ARM: keystone: Switch over to coherent memory address space
With late code patching updates for LPAE machines has merged now and
memblock conversion from bootmem is on its way, Keystone can switch to
the coherent memory address space which starts beyond 4GB boundary.
The idmap alias needs are managed via virt_to_idmap() for boot purpose.
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/platsmp.c')
| -rw-r--r-- | arch/arm/mach-keystone/platsmp.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c index 5cf0683577ea..5f46a7cf907b 100644 --- a/arch/arm/mach-keystone/platsmp.c +++ b/arch/arm/mach-keystone/platsmp.c @@ -17,13 +17,16 @@ #include <linux/io.h> #include <asm/smp_plat.h> +#include <asm/prom.h> +#include <asm/tlbflush.h> +#include <asm/pgtable.h> #include "keystone.h" static int keystone_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned long start = virt_to_phys(&secondary_startup); + unsigned long start = virt_to_idmap(&secondary_startup); int error; pr_debug("keystone-smp: booting cpu %d, vector %08lx\n", @@ -36,6 +39,19 @@ static int keystone_smp_boot_secondary(unsigned int cpu, return error; } +#ifdef CONFIG_ARM_LPAE +static void __cpuinit keystone_smp_secondary_initmem(unsigned int cpu) +{ + pgd_t *pgd0 = pgd_offset_k(0); + cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET); + local_flush_tlb_all(); +} +#else +static inline void __cpuinit keystone_smp_secondary_initmem(unsigned int cpu) +{} +#endif + struct smp_operations keystone_smp_ops __initdata = { .smp_boot_secondary = keystone_smp_boot_secondary, + .smp_secondary_init = keystone_smp_secondary_initmem, }; |