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author | Lennert Buytenhek | 2006-09-16 11:52:02 +0200 |
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committer | Russell King | 2006-09-25 11:25:27 +0200 |
commit | 197c9444d6093b70c8faa24e7ab04a2423c9d14d (patch) | |
tree | 581916e32828c2454c099fdb443e2a7fefc5172e /arch/arm/mach-s3c2410 | |
parent | [ARM] 3813/1: prevent >= 4G /dev/mem mmap() (diff) | |
download | kernel-qcow2-linux-197c9444d6093b70c8faa24e7ab04a2423c9d14d.tar.gz kernel-qcow2-linux-197c9444d6093b70c8faa24e7ab04a2423c9d14d.tar.xz kernel-qcow2-linux-197c9444d6093b70c8faa24e7ab04a2423c9d14d.zip |
[ARM] 3814/1: move 80200 dma_inv_range() erratum check out of line
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
clear the dirty bits, which means that if we invalidate a dirty line,
the dirty data can still be written back to memory later on.
To work around this, dma_inv_range() on these two processors is
implemented as dma_flush_range() (i.e. do a clean D-cache line before
doing the invalidate D-cache line.) For this, we currently have a
processor ID check in xscale_dma_inv_range(), but a better solution
is to add a separate cache_fns and proc_info for A0/A1 80200.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
0 files changed, 0 insertions, 0 deletions