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authorBen Dooks2009-07-31 00:23:36 +0200
committerBen Dooks2009-07-31 00:22:54 +0200
commit25400036867fa7a135fca17810555400d176acaa (patch)
tree218a3194291ed60c482d75932ec7d64cf8109de6 /arch/arm/mach-s3c2412/s3c2412.c
parentARM: S3C: Update CPU register mapping practices. (diff)
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ARM: S3C2412: Update memory register mapping and definitions
Update the mapping of the memory controler registers and add the missing definitions of the register block for the SSMC. The register contents definitions can be found in the pl093 header. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2412/s3c2412.c')
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 5b5aba69ec3f..bef39f77729d 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -69,6 +69,18 @@ static struct map_desc s3c2412_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
IODESC_ENT(WATCHDOG),
+ {
+ .virtual = (unsigned long)S3C2412_VA_SSMC,
+ .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
+ .length = SZ_1M,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = (unsigned long)S3C2412_VA_EBI,
+ .pfn = __phys_to_pfn(S3C2412_PA_EBI),
+ .length = SZ_1M,
+ .type = MT_DEVICE,
+ },
};
/* uart registration process */