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authorKevin Hilman2015-06-11 01:04:48 +0200
committerKevin Hilman2015-06-11 01:04:48 +0200
commit2f69b1a4e8a0569861c5ea55640aba4c95857926 (patch)
tree2b3aa86a2ce9a8a9275ba03e4684d6a704c968b8 /arch/arm/mach-socfpga/platsmp.c
parentARM: Kconfig: Select clocksource in STM32 entry (diff)
parentARM: socfpga: support suspend to ram (diff)
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Merge branch 'socfpga/soc' into next/soc
* socfpga/soc: ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
Diffstat (limited to 'arch/arm/mach-socfpga/platsmp.c')
-rw-r--r--arch/arm/mach-socfpga/platsmp.c36
1 files changed, 35 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 7886eaeb6723..5454e9ce31ea 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -54,6 +54,29 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
return 0;
}
+static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+ if (socfpga_cpu1start_addr) {
+ writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
+ SOCFPGA_A10_RSTMGR_MODMPURST);
+ memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+ writel(virt_to_phys(socfpga_secondary_startup),
+ sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
+
+ flush_cache_all();
+ smp_wmb();
+ outer_clean_range(0, trampoline_size);
+
+ /* This will release CPU #1 out of reset. */
+ writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
+ }
+
+ return 0;
+}
+
static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
@@ -83,10 +106,21 @@ static void socfpga_cpu_die(unsigned int cpu)
cpu_do_idle();
}
-struct smp_operations socfpga_smp_ops __initdata = {
+static struct smp_operations socfpga_smp_ops __initdata = {
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
.smp_boot_secondary = socfpga_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = socfpga_cpu_die,
#endif
};
+
+static struct smp_operations socfpga_a10_smp_ops __initdata = {
+ .smp_prepare_cpus = socfpga_smp_prepare_cpus,
+ .smp_boot_secondary = socfpga_a10_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = socfpga_cpu_die,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
+CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);