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| author | viresh kumar | 2011-02-16 07:40:39 +0100 |
|---|---|---|
| committer | Russell King | 2011-03-09 10:49:45 +0100 |
| commit | af89fd812b00a52c54a3b9b2290fae4d31c7be9a (patch) | |
| tree | 3892de4165b23e98424f672c23b7a6d456ad235d /arch/arm/mach-spear6xx/include | |
| parent | ARM: 6679/1: SPEAr: make clk API functions more generic (diff) | |
| download | kernel-qcow2-linux-af89fd812b00a52c54a3b9b2290fae4d31c7be9a.tar.gz kernel-qcow2-linux-af89fd812b00a52c54a3b9b2290fae4d31c7be9a.tar.xz kernel-qcow2-linux-af89fd812b00a52c54a3b9b2290fae4d31c7be9a.zip | |
ARM: 6703/1: SPEAr: update clk API support
- Add support for divisor per parent clock
- Add ENABLED_ON_INIT feature in clk
- Add clk_set_rate(), round_rate_index & clk_round_rate()
- Simplify clk_recalc functions
- Add/update clock definitions
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear6xx/include')
| -rw-r--r-- | arch/arm/mach-spear6xx/include/mach/misc_regs.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h index d15317788d0d..45571c13227a 100644 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -66,8 +66,8 @@ #define GPT2_CLK_SHIFT 11 #define GPT3_CLK_SHIFT 12 #define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_MASK 0 -#define AUX_CLK_PLL1_MASK 1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ @@ -123,6 +123,7 @@ #define RAS3_CLK_SYNT (MISC_BASE + 0x074) #define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 #define AUX_EQ1_SEL 0 |