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| author | Nicolas Pitre | 2009-03-27 19:22:26 +0100 |
|---|---|---|
| committer | Nicolas Pitre | 2009-03-29 04:39:30 +0200 |
| commit | f000328ac10f23f4841b83ddc60eceb3ba0ac176 (patch) | |
| tree | bcd9597eb25e0285f3d9a61c6203e8ec92d8cdfb /arch/arm/mm/cache-feroceon-l2.c | |
| parent | [ARM] Kirkwood: invalidate L2 cache before enabling it (diff) | |
| download | kernel-qcow2-linux-f000328ac10f23f4841b83ddc60eceb3ba0ac176.tar.gz kernel-qcow2-linux-f000328ac10f23f4841b83ddc60eceb3ba0ac176.tar.xz kernel-qcow2-linux-f000328ac10f23f4841b83ddc60eceb3ba0ac176.zip | |
[ARM] Kirkwood: small L2 code cleanup
Strictly speaking, a MCR instruction does not produce any output.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm/cache-feroceon-l2.c')
| -rw-r--r-- | arch/arm/mm/cache-feroceon-l2.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 1afed5068c2d..6e77c042d8e9 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -258,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) { - int dummy; - - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); + __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); } static int __init invalidate_and_disable_icache(void) |