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| author | Will Deacon | 2012-09-01 06:22:12 +0200 |
|---|---|---|
| committer | Will Deacon | 2012-11-09 15:13:20 +0100 |
| commit | 26ffd0d43b186b0d5186354da8714a1c2d360df0 (patch) | |
| tree | 405c83d298530b65bb64630da52cfb368927691a /arch/arm/mm/proc-v7-3level.S | |
| parent | ARM: mm: introduce L_PTE_VALID for page table entries (diff) | |
| download | kernel-qcow2-linux-26ffd0d43b186b0d5186354da8714a1c2d360df0.tar.gz kernel-qcow2-linux-26ffd0d43b186b0d5186354da8714a1c2d360df0.tar.xz kernel-qcow2-linux-26ffd0d43b186b0d5186354da8714a1c2d360df0.zip | |
ARM: mm: introduce present, faulting entries for PAGE_NONE
PROT_NONE mappings apply the page protection attributes defined by _P000
which translate to PAGE_NONE for ARM. These attributes specify an XN,
RDONLY pte that is inaccessible to userspace. However, on kernels
configured without support for domains, such a pte *is* accessible to
the kernel and can be read via get_user, allowing tasks to read
PROT_NONE pages via syscalls such as read/write over a pipe.
This patch introduces a new software pte flag, L_PTE_NONE, that is set
to identify faulting, present entries.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-v7-3level.S')
| -rw-r--r-- | arch/arm/mm/proc-v7-3level.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index d23d067e1904..7b56386f9496 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -67,6 +67,9 @@ ENTRY(cpu_v7_set_pte_ext) #ifdef CONFIG_MMU tst r2, #L_PTE_VALID beq 1f + tst r3, #1 << (57 - 32) @ L_PTE_NONE + bicne r2, #L_PTE_VALID + bne 1f tst r3, #1 << (55 - 32) @ L_PTE_DIRTY orreq r2, #L_PTE_RDONLY 1: strd r2, r3, [r0] |