diff options
| author | Ben Dooks | 2008-10-21 15:06:20 +0200 |
|---|---|---|
| committer | Ben Dooks | 2008-12-15 22:45:42 +0100 |
| commit | b2a6cf3b1e099a724504ba16a4c9aea1eb0122a6 (patch) | |
| tree | 32e898703506e2d90a5e7f4545bca44e13678388 /arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c | |
| parent | Merge git://git.marvell.com/orion into devel (diff) | |
| download | kernel-qcow2-linux-b2a6cf3b1e099a724504ba16a4c9aea1eb0122a6.tar.gz kernel-qcow2-linux-b2a6cf3b1e099a724504ba16a4c9aea1eb0122a6.tar.xz kernel-qcow2-linux-b2a6cf3b1e099a724504ba16a4c9aea1eb0122a6.zip | |
[ARM] S3C24XX: Default SPI pin configuration for SPI
Add a set of default pin configuration routines for
setting up the SPI gpio configuration when using the
hardware SPI driver.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c')
| -rw-r--r-- | arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c new file mode 100644 index 000000000000..8fccd4e549f0 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> + +#include <mach/hardware.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, + int enable) +{ + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); + s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); + s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); + s3c2410_gpio_pullup(S3C2410_GPG5, 0); + s3c2410_gpio_pullup(S3C2410_GPG6, 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPG5, 1); + s3c2410_gpio_pullup(S3C2410_GPG6, 1); + s3c2410_gpio_pullup(S3C2410_GPG7, 1); + } +} |