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| author | Suzuki K Poulose | 2018-03-26 16:12:49 +0200 |
|---|---|---|
| committer | Will Deacon | 2018-03-26 19:01:44 +0200 |
| commit | ece1397cbc89c51914fae1aec729539cfd8bd62b (patch) | |
| tree | 32e396f96ffcd188ad30d40e73c609d723f89ced /arch/arm64/Kconfig | |
| parent | arm64: Delay enabling hardware DBM feature (diff) | |
| download | kernel-qcow2-linux-ece1397cbc89c51914fae1aec729539cfd8bd62b.tar.gz kernel-qcow2-linux-ece1397cbc89c51914fae1aec729539cfd8bd62b.tar.xz kernel-qcow2-linux-ece1397cbc89c51914fae1aec729539cfd8bd62b.zip | |
arm64: Add work around for Arm Cortex-A55 Erratum 1024718
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to skip enabling the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected. There are some other cores suffering from this
errata, which could be added to the midr_list to trigger the work
around.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: ckadabi@codeaurora.org
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/Kconfig')
| -rw-r--r-- | arch/arm64/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a6688fcf3dc6..fd74c5830232 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -465,6 +465,20 @@ config ARM64_ERRATUM_843419 If unsure, say Y. +config ARM64_ERRATUM_1024718 + bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" + default y + help + This option adds work around for Arm Cortex-A55 Erratum 1024718. + + Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect + update of the hardware dirty bit when the DBM/AP bits are updated + without a break-before-make. The work around is to disable the usage + of hardware DBM locally on the affected cores. CPUs not affected by + erratum will continue to use the feature. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y |