diff options
| author | Sudeep Holla | 2017-04-13 11:05:38 +0200 |
|---|---|---|
| committer | Sudeep Holla | 2017-04-19 13:16:51 +0200 |
| commit | f9936c4abf63106e0bcc3d82098dd1cfc3dc5290 (patch) | |
| tree | 28ef7e862ba6d00ee8323ffcba5300e26bdf7c11 /arch/arm64/boot/dts/arm/juno-r2.dts | |
| parent | arm64: dts: juno: fix few unit address format warnings (diff) | |
| download | kernel-qcow2-linux-f9936c4abf63106e0bcc3d82098dd1cfc3dc5290.tar.gz kernel-qcow2-linux-f9936c4abf63106e0bcc3d82098dd1cfc3dc5290.tar.xz kernel-qcow2-linux-f9936c4abf63106e0bcc3d82098dd1cfc3dc5290.zip | |
arm64: dts: juno: add information about L1 and L2 caches
Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.
Commit 9a802431c527 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.
This patch adds the information about L1 and L2 caches on all variants
of Juno platform.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/juno-r2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-r2.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 218d0e4736a8..405e2fba025b 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -89,6 +89,12 @@ reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -100,6 +106,12 @@ reg = <0x0 0x1>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -111,6 +123,12 @@ reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -122,6 +140,12 @@ reg = <0x0 0x101>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -133,6 +157,12 @@ reg = <0x0 0x102>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -144,6 +174,12 @@ reg = <0x0 0x103>; device_type = "cpu"; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -152,10 +188,16 @@ A72_L2: l2-cache0 { compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; A53_L2: l2-cache1 { compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; |