diff options
| author | Xiaowei Song | 2017-06-16 16:13:22 +0200 |
|---|---|---|
| committer | Wei Xu | 2017-06-16 16:30:39 +0200 |
| commit | 96909778f8929f9275b6b163be051f2bcbe4d3e7 (patch) | |
| tree | 2748c0a61ea3a284fd2f9315c950fdd65c415714 /arch/arm64/boot/dts/hisilicon/hi3660.dtsi | |
| parent | dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs (diff) | |
| download | kernel-qcow2-linux-96909778f8929f9275b6b163be051f2bcbe4d3e7.tar.gz kernel-qcow2-linux-96909778f8929f9275b6b163be051f2bcbe4d3e7.tar.xz kernel-qcow2-linux-96909778f8929f9275b6b163be051f2bcbe4d3e7.zip | |
arm64: dts: hisi: add kirin pcie node
Add PCIe node for hi3660
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Changes in v5:
* fix interrupt-map, to conform to gic's #address-cells = <0>
* remove redundant status = "ok"
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hi3660.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index e138973024c5..8183d71bcd59 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -754,5 +754,41 @@ cs-gpios = <&gpio18 5 0>; status = "disabled"; }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; }; }; |