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| author | Zhangfei Gao | 2017-08-16 09:26:35 +0200 |
|---|---|---|
| committer | Wei Xu | 2017-08-16 10:31:01 +0200 |
| commit | 94d2d94b40ca88b558af8a1d4b091f5027efb271 (patch) | |
| tree | 587493c3700ed1765fb813cec1fe9e6bf1ee3092 /arch/arm64/boot/dts/hisilicon/hi6220.dtsi | |
| parent | arm64: dts: hisi: add PCIe host controller node for hip07 SoC (diff) | |
| download | kernel-qcow2-linux-94d2d94b40ca88b558af8a1d4b091f5027efb271.tar.gz kernel-qcow2-linux-94d2d94b40ca88b558af8a1d4b091f5027efb271.tar.xz kernel-qcow2-linux-94d2d94b40ca88b558af8a1d4b091f5027efb271.zip | |
arm64: dts: hi6220: add acpu_sctrl
Add acpu_sctrl clock node
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hi6220.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index eacbe0db5bc2..f8012d51400a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -262,6 +262,12 @@ #clock-cells = <1>; }; + acpu_sctrl: acpu_sctrl@f6504000 { + compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; + reg = <0x0 0xf6504000 0x0 0x1000>; + #clock-cells = <1>; + }; + medianoc_ade: medianoc_ade@f4520000 { compatible = "syscon"; reg = <0x0 0xf4520000 0x0 0x4000>; |