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| author | Gregory CLEMENT | 2018-03-14 17:19:26 +0100 |
|---|---|---|
| committer | Gregory CLEMENT | 2018-03-19 17:13:47 +0100 |
| commit | 3c7f7f1503d20b14e22f64c27dc13522f5d60707 (patch) | |
| tree | 5307e26bb4c4f8b404d054ef3a5796bed24ababe /arch/arm64/boot/dts/marvell | |
| parent | ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node (diff) | |
| download | kernel-qcow2-linux-3c7f7f1503d20b14e22f64c27dc13522f5d60707.tar.gz kernel-qcow2-linux-3c7f7f1503d20b14e22f64c27dc13522f5d60707.tar.xz kernel-qcow2-linux-3c7f7f1503d20b14e22f64c27dc13522f5d60707.zip | |
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node
This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "crypto: inside-secure - fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index c491adc90b8c..b6947fcb8ce6 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -402,7 +402,9 @@ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; - clocks = <&CP110_LABEL(clk) 1 26>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 26>, + <&CP110_LABEL(clk) 1 17>; dma-coherent; }; }; |