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| author | Gregory CLEMENT | 2018-02-15 14:44:23 +0100 |
|---|---|---|
| committer | Gregory CLEMENT | 2018-02-27 17:47:48 +0100 |
| commit | c137ba9b41c739ae7992921182ba94b0b7d52e82 (patch) | |
| tree | 4fa4dfc36aebd947ba6e84b135cdb91a4a2c6017 /arch/arm64/boot/dts/marvell | |
| parent | arm64: dts: marvell: armada-8080-db: use SPDX-License-Identifier (diff) | |
| download | kernel-qcow2-linux-c137ba9b41c739ae7992921182ba94b0b7d52e82.tar.gz kernel-qcow2-linux-c137ba9b41c739ae7992921182ba94b0b7d52e82.tar.xz kernel-qcow2-linux-c137ba9b41c739ae7992921182ba94b0b7d52e82.zip | |
ARM64: dts: marvell: armada-cp110: Add registers clock for sata node
This extra clock is needed to access the registers of the AHCI SATA
controller used on the Armada 7K/8K SoCs.
The ahci drivers was already designed to support up to 5 clocks so there
is only need to update the device tree to use it. It was not noticed
until now because of wrong assumption in the clock drivers, but as this
IP really needs 2 clocks, we had to declare both of them.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 0709b19eb328..215cdc65447c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -230,7 +230,8 @@ "generic-ahci"; reg = <0x540000 0x30000>; interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CP110_LABEL(clk) 1 15>; + clocks = <&CP110_LABEL(clk) 1 15>, + <&CP110_LABEL(clk) 1 16>; status = "disabled"; }; |