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| author | Harunobu Kurokawa | 2018-06-04 19:49:08 +0200 |
|---|---|---|
| committer | Simon Horman | 2018-06-25 15:30:28 +0200 |
| commit | 51933b101567692b3a2a8e6d9e06883985c79724 (patch) | |
| tree | a32016a7e1b133f1f5996d4b275c0efe32322667 /arch/arm64/boot/dts/renesas/r8a7796.dtsi | |
| parent | arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core (diff) | |
| download | kernel-qcow2-linux-51933b101567692b3a2a8e6d9e06883985c79724.tar.gz kernel-qcow2-linux-51933b101567692b3a2a8e6d9e06883985c79724.tar.xz kernel-qcow2-linux-51933b101567692b3a2a8e6d9e06883985c79724.zip | |
arm64: dts: renesas: r8a7796: Add PCIe device nodes
This patch adds PCIe{0,1} device nodes for R8A7796 SoC.
Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 50 |
1 files changed, 47 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 7c25be6b5af3..2a04635bc9ae 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7796 SoC * - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2017 Renesas Electronics Corp. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -2108,13 +2108,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; imr-lx4@fe860000 { |