diff options
| author | Caesar Wang | 2016-07-27 16:24:06 +0200 |
|---|---|---|
| committer | Jonathan Cameron | 2016-08-23 20:08:21 +0200 |
| commit | 78ec79bfd59e126e1cb394302bfa531a420b3ecd (patch) | |
| tree | 355a1db225db7a09ffe886165933f9df2b7e1091 /arch/arm64/boot/dts/rockchip/rk3368.dtsi | |
| parent | iio: adc: rockchip_saradc: reset saradc controller before programming it (diff) | |
| download | kernel-qcow2-linux-78ec79bfd59e126e1cb394302bfa531a420b3ecd.tar.gz kernel-qcow2-linux-78ec79bfd59e126e1cb394302bfa531a420b3ecd.tar.xz kernel-qcow2-linux-78ec79bfd59e126e1cb394302bfa531a420b3ecd.zip | |
arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3368.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d02a900378e1..4f44d1191bfd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -270,6 +270,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; |