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| author | Will Deacon | 2016-09-22 12:25:25 +0200 |
|---|---|---|
| committer | Will Deacon | 2017-02-09 19:31:25 +0100 |
| commit | 2bf47e194608192b7346baea1d57929a87ced3f9 (patch) | |
| tree | ac7aebfccf4d312cf1d20293b94a9e145d1c69aa /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64: arch_timer: document Hisilicon erratum 161010101 (diff) | |
| download | kernel-qcow2-linux-2bf47e194608192b7346baea1d57929a87ced3f9.tar.gz kernel-qcow2-linux-2bf47e194608192b7346baea1d57929a87ced3f9.tar.xz kernel-qcow2-linux-2bf47e194608192b7346baea1d57929a87ced3f9.zip | |
arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2
The SPE architecture requires each exception level to enable access
to the SPE controls for the exception level below it, since additional
context-switch logic may be required to handle the buffer safely.
This patch allows EL1 (host) access to the SPE controls when entered at
EL2.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
0 files changed, 0 insertions, 0 deletions