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| author | Marc Zyngier | 2018-09-27 18:15:34 +0200 |
|---|---|---|
| committer | Catalin Marinas | 2018-10-01 14:38:47 +0200 |
| commit | 95b861a4a6d94f64d5242605569218160ebacdbe (patch) | |
| tree | 201e6c1b33483438a87a7f2a030477bd41f82312 /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64: compat: Add CNTFRQ trap handler (diff) | |
| download | kernel-qcow2-linux-95b861a4a6d94f64d5242605569218160ebacdbe.tar.gz kernel-qcow2-linux-95b861a4a6d94f64d5242605569218160ebacdbe.tar.xz kernel-qcow2-linux-95b861a4a6d94f64d5242605569218160ebacdbe.zip | |
arm64: arch_timer: Add workaround for ARM erratum 1188873
When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.
This only affects versions r0p0, r1p0 and r2p0 of the CPU.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 6eb1b3fd0493..6e2d254c09eb 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -53,7 +53,8 @@ #define ARM64_HAS_STAGE2_FWB 32 #define ARM64_HAS_CRC32 33 #define ARM64_SSBS 34 +#define ARM64_WORKAROUND_1188873 35 -#define ARM64_NCAPS 35 +#define ARM64_NCAPS 36 #endif /* __ASM_CPUCAPS_H */ |