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| author | Catalin Marinas | 2014-04-03 18:48:54 +0200 |
|---|---|---|
| committer | Catalin Marinas | 2014-05-09 16:47:45 +0200 |
| commit | a41dc0e841523efe1df7fa5ad48b5e9027a921df (patch) | |
| tree | c162086a45807902dd8c510132f3c3f82603d3e6 /arch/arm64/include/asm/esr.h | |
| parent | Linux 3.15-rc4 (diff) | |
| download | kernel-qcow2-linux-a41dc0e841523efe1df7fa5ad48b5e9027a921df.tar.gz kernel-qcow2-linux-a41dc0e841523efe1df7fa5ad48b5e9027a921df.tar.xz kernel-qcow2-linux-a41dc0e841523efe1df7fa5ad48b5e9027a921df.zip | |
arm64: Implement cache_line_size() based on CTR_EL0.CWG
The hardware provides the maximum cache line size in the system via the
CTR_EL0.CWG bits. This patch implements the cache_line_size() function
to read such information, together with a sanity check if the statically
defined L1_CACHE_BYTES is smaller than the hardware value.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/esr.h')
0 files changed, 0 insertions, 0 deletions