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| author | Julien Thierry | 2017-10-25 11:04:33 +0200 |
|---|---|---|
| committer | Will Deacon | 2017-10-25 12:57:33 +0200 |
| commit | 6436beeee5721a8e906e9eabf866f12d04470437 (patch) | |
| tree | 022956462f870882d483fe09492a0c2f679d61eb /arch/arm64/kernel/cpufeature.c | |
| parent | arm64: Use existing defines for mdscr (diff) | |
| download | kernel-qcow2-linux-6436beeee5721a8e906e9eabf866f12d04470437.tar.gz kernel-qcow2-linux-6436beeee5721a8e906e9eabf866f12d04470437.tar.xz kernel-qcow2-linux-6436beeee5721a8e906e9eabf866f12d04470437.zip | |
arm64: Fix single stepping in kernel traps
Software Step exception is missing after stepping a trapped instruction.
Ensure SPSR.SS gets set to 0 after emulating/skipping a trapped instruction
before doing ERET.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[will: replaced AARCH32_INSN_SIZE with 4]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4d9243969702..250e8cfff67d 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1296,7 +1296,7 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) if (!rc) { dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); pt_regs_write_reg(regs, dst, val); - regs->pc += 4; + arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); } return rc; |