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| author | Catalin Marinas | 2012-03-05 12:49:32 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2012-09-17 14:42:13 +0200 |
| commit | 53631b54c8704fe5de435582c82ddbc0bfabf06a (patch) | |
| tree | 3bca49152b4e2eeaf7a96f2405ed963ce17da1e5 /arch/arm64/kernel/hw_breakpoint.c | |
| parent | arm64: 32-bit (compat) applications support (diff) | |
| download | kernel-qcow2-linux-53631b54c8704fe5de435582c82ddbc0bfabf06a.tar.gz kernel-qcow2-linux-53631b54c8704fe5de435582c82ddbc0bfabf06a.tar.xz kernel-qcow2-linux-53631b54c8704fe5de435582c82ddbc0bfabf06a.zip | |
arm64: Floating point and SIMD
This patch adds support for FP/ASIMD register bank saving and restoring
during context switch and FP exception handling to generate SIGFPE.
There are 32 128-bit registers and the context switching is currently
done non-lazily. Benchmarks on real hardware are required before
implementing lazy FP state saving/restoring.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm64/kernel/hw_breakpoint.c')
0 files changed, 0 insertions, 0 deletions