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| author | Thomas Gleixner | 2015-10-11 10:04:51 +0200 |
|---|---|---|
| committer | Thomas Gleixner | 2015-10-11 10:04:51 +0200 |
| commit | fcf8ab690e3decf8335c51fdabea773a3f5ea026 (patch) | |
| tree | 5f0a1c9211947e817be6f499f1491a4bbf1573d9 /arch/arm64/kernel | |
| parent | irqchip/sunxi-nmi: Switch to of_io_request_and_map() from of_iomap() (diff) | |
| parent | arm/arm64: KVM: Only allow 64bit hosts to build VGICv3 (diff) | |
| download | kernel-qcow2-linux-fcf8ab690e3decf8335c51fdabea773a3f5ea026.tar.gz kernel-qcow2-linux-fcf8ab690e3decf8335c51fdabea773a3f5ea026.tar.xz kernel-qcow2-linux-fcf8ab690e3decf8335c51fdabea773a3f5ea026.zip | |
Merge tag 'gic-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
GIC updates for Linux 4.4 from Marc Zyngier:
- Enable basic GICv3 support on 32bit ARM (mostly for running VMs with
more than 8 virtual CPUs)
- arm64 changes to deal with firmware limitations that forces a GICv3
to be used as a GICv2
- A GICv2m erratum workaround on Applied Micro X-Gene2
Diffstat (limited to 'arch/arm64/kernel')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 19 | ||||
| -rw-r--r-- | arch/arm64/kernel/head.S | 2 |
2 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3c9aed32f70b..305f30dc9e63 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -23,6 +23,8 @@ #include <asm/cpufeature.h> #include <asm/processor.h> +#include <linux/irqchip/arm-gic-v3.h> + static bool feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) { @@ -45,11 +47,26 @@ __ID_FEAT_CHK(id_aa64pfr0); __ID_FEAT_CHK(id_aa64mmfr1); __ID_FEAT_CHK(id_aa64isar0); +static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry) +{ + bool has_sre; + + if (!has_id_aa64pfr0_feature(entry)) + return false; + + has_sre = gic_enable_sre(); + if (!has_sre) + pr_warn_once("%s present but disabled by higher exception level\n", + entry->desc); + + return has_sre; +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, - .matches = has_id_aa64pfr0_feature, + .matches = has_useable_gicv3_cpuif, .field_pos = 24, .min_field_value = 1, }, diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 90d09eddd5b2..351a4de1b1e2 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -498,6 +498,8 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 msr_s ICC_SRE_EL2, x0 isb // Make sure SRE is now set + mrs_s x0, ICC_SRE_EL2 // Read SRE back, + tbz x0, #0, 3f // and check that it sticks msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 3: |