diff options
| author | Will Deacon | 2018-02-02 18:31:39 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2018-02-06 23:53:44 +0100 |
| commit | 5dfc6ed27710c42cbc15db5c0d4475699991da0a (patch) | |
| tree | b2cb8fd601a5694ce4992354dc83c0fbd6e2f459 /arch/arm64/mm | |
| parent | arm64: futex: Mask __user pointers prior to dereference (diff) | |
| download | kernel-qcow2-linux-5dfc6ed27710c42cbc15db5c0d4475699991da0a.tar.gz kernel-qcow2-linux-5dfc6ed27710c42cbc15db5c0d4475699991da0a.tar.xz kernel-qcow2-linux-5dfc6ed27710c42cbc15db5c0d4475699991da0a.zip | |
arm64: entry: Apply BP hardening for high-priority synchronous exceptions
Software-step and PC alignment fault exceptions have higher priority than
instruction abort exceptions, so apply the BP hardening hooks there too
if the user PC appears to reside in kernel space.
Reported-by: Dan Hettena <dhettena@nvidia.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/fault.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index af530eb9f2ed..43b28a782ed4 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -732,6 +732,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr, struct siginfo info; struct task_struct *tsk = current; + if (user_mode(regs)) { + if (instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + local_irq_enable(); + } + if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS)) pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n", tsk->comm, task_pid_nr(tsk), @@ -791,6 +797,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr, if (interrupts_enabled(regs)) trace_hardirqs_off(); + if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + if (!inf->fn(addr, esr, regs)) { rv = 1; } else { |