diff options
| author | Douglas Anderson | 2016-06-20 19:56:48 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2016-06-22 18:24:05 +0200 |
| commit | 64e3481c8ab187a42b68048dbd321e54d182e762 (patch) | |
| tree | e5d6e7c15a3c61eabf003b64cb6805946fb2f4ec /arch/arm64 | |
| parent | arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368 (diff) | |
| download | kernel-qcow2-linux-64e3481c8ab187a42b68048dbd321e54d182e762.tar.gz kernel-qcow2-linux-64e3481c8ab187a42b68048dbd321e54d182e762.tar.xz kernel-qcow2-linux-64e3481c8ab187a42b68048dbd321e54d182e762.zip | |
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ef472e29f037..9833c7da5256 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -229,6 +229,7 @@ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; |