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| author | Will Deacon | 2016-03-01 00:15:44 +0100 |
|---|---|---|
| committer | Will Deacon | 2016-03-01 00:23:59 +0100 |
| commit | fe638401a091f4473e9e30942ea3cecc0c0b2b94 (patch) | |
| tree | dfb46b779a57a03f05a76423b6122b578a55e359 /arch/arm64 | |
| parent | arm-cci: remove unused variable (diff) | |
| download | kernel-qcow2-linux-fe638401a091f4473e9e30942ea3cecc0c0b2b94.tar.gz kernel-qcow2-linux-fe638401a091f4473e9e30942ea3cecc0c0b2b94.tar.xz kernel-qcow2-linux-fe638401a091f4473e9e30942ea3cecc0c0b2b94.zip | |
arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC
Commit 7175f0591eb9 ("arm64: perf: Enable PMCR long cycle counter bit")
added initial support for a 64-bit cycle counter enabled using PMCR.LC.
Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any
attempts to set the enable bit are ignored by armv8pmu_pmcr_write.
This patch extends the mask to include the new bit.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/perf_event.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 1cc61fc321d9..c4c97655662e 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -408,7 +408,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = { #define ARMV8_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ #define ARMV8_PMCR_N_MASK 0x1f -#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ +#define ARMV8_PMCR_MASK 0x7f /* Mask for writable bits */ /* * PMOVSR: counters overflow flag status reg |