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| author | Greg Ungerer | 2010-11-09 04:35:55 +0100 |
|---|---|---|
| committer | Greg Ungerer | 2011-01-05 06:19:18 +0100 |
| commit | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (patch) | |
| tree | d478523ee8bec4ecc638c9f9a35816fc12aaa37f /arch/m68k/include/asm/m53xxacr.h | |
| parent | m68knommu: move inclusion of ColdFire v4 cache registers (diff) | |
| download | kernel-qcow2-linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.gz kernel-qcow2-linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.xz kernel-qcow2-linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.zip | |
m68knommu: clean up ColdFire cache control code
The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m53xxacr.h')
| -rw-r--r-- | arch/m68k/include/asm/m53xxacr.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 532fbb91185f..74c81c9b177e 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -48,5 +48,23 @@ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This default in the + * CACR is cache inhibited, we use the ACR register to set cacheing + * enabled on the regions we want (eg RAM). + */ +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) +#else +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) +#endif + +#define CACHE_INIT CACR_CINVA + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m53xxsim_h */ |